1. Field of Invention
The present invention relates to integrated circuits and more particularly to parametric perturbation analysis of performance metrics for integrated circuits, especially for applications related to statistical timing analysis of combinational logic cells.
2. Description of Related Art
The problem of digital circuit (static) timing analysis under statistical process variation has recently received considerable attention from the academic community. Numerous approaches to “statistical timing” of general combinational logic circuits [1, 2, 3, 5, 6] as well as specialized cases such as clock networks [7] have been proposed. With increasing importance of process variation effects, the hope is that by moving to statistically based methods, as opposed to corner-based methodologies, several advantages will be gained. By means of more realistic timing analysis, an overly pessimistic design due to unrealistic rare corner cases can be avoided. Particularly when considering interconnect variation and inter-die variation, the number of corners that must be analyzed can be very large, leading to excessive analysis times. Finally, some problems due to intra-die variation are difficult to capture at all in a purely corner-based methodology.
In some operational settings black-box techniques such as response surface models (RSMs) have been applied to problems in statistical static timing analysis [13]. However these methods are often ill-suited to problems where a large number (>>10) of independent process variables are involved. An example of such a case is MOS parameter mismatch, where parameters can vary stochastically from device to device, leading to several independent variables per transistor. An example at the path or block level of analysis is intra-die variation in interconnect, because of the potentially large number of interconnect layers.
Before the advantages of statistical timing can be realized, the underlying components of the digital timing analysis flow—parasitic extraction, cell characterization, cell delay computation, and interconnect reduction—must be evolved to suit the requirements of the new timing analyzers [1]. Some work has appeared along this line; for example, several approaches have been proposed for interconnect reduction under process variation [8, 9, 10, 11]. However, problems related to cell library generation and related parametric variations have received relatively little attention.
Thus, there is a need for improved methods for analyzing parametric perturbations of performance metrics for integrated circuits, especially for applications related to statistical timing analysis of combinational logic cells.